1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device for exchanging signals with the outside in synchronization with a clock signal applied periodically from the outside.
2. Description of the Background Art
In memory application systems, speed of operation of a dynamic random access memory (hereinafter referred to as DRAM) used as a main memory has been increased. The speed of operation, however, has not yet sufficiently follow the speed of operation of a microprocessor (hereinafter referred to as an MPU). This is said to be a cause of lower performance of the overall system, with access time and cycle time of the DRAM being a bottleneck. Recently, various high speed DRAMs operating in synchronization with an external clock signal have been proposed as main memory for a high speed MPU.
Configuration and operation of a synchronous dynamic random access memory (hereinafter referred to as an SDRAM) as a representative among these will be briefly described in the following. The SDRAM is capable of high speed access to a prescribed number of continuous bits in synchronization with a system clock signal.
FIG. 14 is a timing chart representing a standard operation of the SDRAM.
FIG. 14 shows operation timings when continuous 8 bits of data are written and read to and from the SDRAM.
Referring to FIG. 14, at a rising edge of an external clock signal ext.CLK, which is a system clock, at time t1, the SDRAM takes a row address signal Xa in response to external control signals, that is, a chip select signal /CS and a row address strobe signal /RAS both at an active state (logical low, "L" level).
Thereafter, at time t2, in response to the chip select signal /CS and the column address strobe signal /CAS being at the active state ("L" level), reading operation is designated, and a column address signal Yb is taken.
More specifically, an address signal Add. is time-divisionally multiplexed as row address signal Xa and column address signal Yb, and applied to the SDRAM.
In accordance with the row address signal Xa and the column address signal Yb taken in this manner, row and column selecting operations take place in the SDRAM.
After a cycle corresponding to CAS latency (in the example of FIG. 14, three clock cycles), at time t3, first data is output. Thereafter, in response to the rise of the clock signal CLK, data is output from the SDRAM in each cycle from time t4 to t10. The number of bits read continuously here is referred to as burst length, and in FIG. 14, the burst length is 8.
At time t8, in response to the chip select signal ICS, the row address strobe signal /RAS and a write enable signal /WE all at the active state ("L" level), precharge operation is designated.
Thereafter, in a writing operation, at time t10, in response to the chip select signal /CS and the row address strobe signal /RAS both at the active state, a row address signal Xc is taken.
Thereafter, at time t11, when chip select signal /CS, column address strobe signal /CAS and write enable signal /WE are all at the active state of "L" level, a write operation is designated, a column address signal Yd is taken, and data d0 applied at that time is taken as first write data to the SDRAM.
In this manner, row and column selecting operations are performed in response to the fall of signals /RAS and /CAS in the SDRAM.
In cycles from t12 to 18, 8 bits of input data d1, . . . , d7 are taken successively in synchronization with an internal clock signal CLK, and the input data are successively written to the memory cells.
In a conventional common DRAM, operations of taking address signals and input data are synchronized with external control signals, that is, row address strobe signal /RAS and column address strobe signal /CAS. By contrast, in the SDRAM, external signals such as the address strobe signals /RAS, /CAS, address signals and input data are taken at a rising edge of an externally applied external clock signal ext.CLK which is, for example, a system clock.
Further, in the SDRAM, memory cells contained therein are operated divided into a plurality of banks, as will be described later. The configuration in which the internal memory cell array is divided into a plurality of banks makes it possible for the banks to perform activating operation (for example, raising of potential level of a word line, activation of a sense amplifier), inactivating operation (lowering of the word line level, inactivation of the sense amplifier) and a precharge operation, almost independent from each other.
In the following, an SDRAM of 2 bank configuration will be described as an example.
In a common DRAM, a precharge operation is indispensable before every access. This is a cause that makes the cycle time in a read or write operation of the common DRAM almost twice the access time.
In the SDRAM with the inside divided into a plurality of banks, however, if a bank 1 is being accessed while a bank 2 is precharged, it is possible to access bank 2 without any precharge time.
In this manner, it becomes possible to eliminate loss time derived from precharging, by alternately accessing/precharging banks 1 and 2. In other words, this is the interleave operation conventionally utilized externally on a plurality of DRAM devices incorporated into the internal operation of the SDRAM chip.
FIG. 15 is a schematic diagram showing a configuration of a conventional word driver, FIG. 16 is a schematic diagram showing a configuration of a conventional RX decoder, and FIG. 17 is a schematic diagram showing a configuration corresponding to a column of memory cells.
Referring first to FIG. 15, predecoded address signals Xj, Xk and Xl are input to a decoder 800. Predecode signal Xj is input to the gate of P channel MOS transistor P11 and the gate of N channel MOS transistor N11. N channel MOS transistor N12 receives predecode signal Xk at its gate. Further, predecode signal X1 is supplied to the gate of N channel MOS transistor N13.
At a standby state, predecode signals Xj, Xk and Xl are all at the "L" level. Accordingly, a P channel MOS transistor P11 is rendered conductive, and a node n11 is precharged to a power supply potential Vdd.
In response, a signal output from an inverter 802 is at the "L" level, and therefore in a word driver 820 corresponding to a word line WL0, with an N channel MOS transistor QD1 receiving at its gate the power supply potential Vdd and receiving at one of its source/drain the output from inverter 802 interposed, a node n21, that is, the gate of a transistor QW1 attains to the "L" level.
N channel MOS transistor QW1 has its drain connected to RX0 among common word lines RX0 to RX3, and an N channel MOS transistor QL1 is provided between the source of transistor QW1 and a ground potential. At a connection node between transistors QW1 and QL1, word line WL0 is connected. Transistor QL1 receives at its gate potential level of node n11.
Word drivers 830 to 850 provided corresponding to other word lines WL1 to WL3, respectively, basically have the same configuration as word driver 820 except that the word drivers are connected to different common word lines.
An exemplary circuit of a typical RX driver 700 is shown in FIG. 16. A capacitance Cb for boosting is provided, with one end of the capacitance Cb driven by a signal RXP obtained by delaying an RX trigger signal RXT itself by a delay circuit 704. Because of capacitive coupling, potential level at the other end of capacitance Cb is boosted to be Vcc+Vthm (Vthm:threshold voltage of memory cell transistor NA) or higher. The potential level of the aforementioned the other end of the capacitance Cb is transmitted to a node RX through a transistor 706 operating as a diode. A decode circuit 750 decodes an address signal (for example, lower bits A0 and Al), and selects any of transistors 710, 720, 730 and 740, and in response, any of transistors 712, 722, 732 and 742 is rendered conductive. The potential level of node RX is transmitted as signals RX0 to RX3 through the selected one of the transistors 712, 722, 732 and 742.
Referring to FIG. 17, the memory cell capacitor Cp receives a cell plate potential Vcp generated in the SDRAM at one end, and connected at the other end to a bit line BL through an access transistor NA. The transistor NA has its gate connected to a corresponding word line WL.
A sense amplifier 860 is provided for a pair of bit lines BL and /BL complementary to each other. Sense amplifier 860 includes an N channel sense amplifier 910 which is activated when the ground potential GND is supplied through a transistor QN receiving at its gate a signal S0N, and a P channel sense amplifier 920 which is activated when the power supply potential Vdd is supplied through a transistor Qp receiving at its gate a sense amplifier activating signal /S0P. Further, corresponding to the pair of bit lines BL and /BL, a precharge circuit 930 activated by a signal BLEQ for holding potentials of the pair of bit lines at the same potential level Vdd/2 and a column selection gate 940 activated by a column selection line CSL for connecting corresponding I/O line pair I/O, /I/O to the bit line pair BL, /BL are provided.
Operations of the word driver and the sense amplifier of the conventional SDRAM shown in FIGS. 15, 16 and 17 will be described with reference to FIG. 18.
Generally, a bank in the SDRAM is activated by an ACT command applied externally. More specifically, at a rising edge of external clock signal ext.CLK at time t0, for example, if chip select signal /CS and row address strobe signal /RAS are both at the "L" level and column address strobe signal /CAS and write enable signal /WE are both at the "H" level, the SDRAM recognizes that the ACT command is applied.
In this case, at time t1, internal row address strobe signal int.RAS in the SDRAM attains to the "H" level, and the address signal at that time point is taken in the SDRAM as a row address signal X.
The row address signal is latched in the SDRAM, and established as internal row address signals RAD and /RAD (in the following, the internal row address will be generally referred to as signals RAD and /RAD).
When internal row address signals RAD and /RAD are established, the address signal is predecoded by the predecoder, and predecode signals Xj, Xk and Xl are generated.
When any of the word drivers is selected in accordance with the predecode signals Xj, Xk and Xl input to decoder 800, potential level of a node n21 in the word driver attains to Vdd-Vth1 (where Vth1 represents threshold voltage of transistor DQ1).
Thereafter, based on the internal row address strobe signal int.RAS, a potential boosted to be not lower than (Vdd+Vthm) (where Vthm represents threshold voltage of memory cell transistor NA) by the RX trigger signal RXT obtained by delaying the internal row address strobe signal until the time point t2, is applied to any of the common word lines RX.
When common word line RX0 is set to the selected state among common word lines RX0 to RX3, by a coupling between node n21 and the common word line resulting from gate capacitance of transistor QW1, potential level of node n21 attains to Vdd+Vthm+Vth2 (where potential Vth2 represents threshold voltage of transistor QW1) or higher, and the potential of the selected common word line RX0 is transmitted with the level maintained as it is, to the selected word line WL0, for example.
Accordingly, when stored data is read from a memory cell MC to a bit line BL, there is not a potential drop corresponding to the threshold voltage of access transistor NA, and therefore S/N in data reading from the memory cell is improved.
When the potential level of the word line rises, potential level of bit line BL which has been precharged to Vdd/2 in advance changes in accordance with the data stored in the memory cell MC.
Thereafter, by a sense amplifier activating signal S0N obtained by delaying the signal RXT to time t3 and a sense amplifier activating signal /S0P obtained by delaying the signal RXT to time t4, transistors QN and QP in sense amplifier 900 are rendered conductive successively, and by sense amplifier 900, data appearing on the bit lines is amplified.
FIG. 18 shows an example in which "H" level data is stored in the memory cell MC.
When an external Write command or a Read command is input, a column address signal Y is taken at that time point.
By a signal obtained by internally decoding column address signal Y, column selection signal CSL corresponding to the selected column of memory cells is activated, and bit line BL is connected to data input/output line pair I/O, whereby data is written or read.
The inactivating operation of the SDRAM takes place when a PCG command (precharge command) is input externally. More specifically, at a rising edge of external clock signal ext.CLK, if chip select signal CS, row address strobe signal /RAS and write enable signal /WL are all at the "L" level and column address strobe signal /CAS is at the "H" level, then at time t5, internal row address strobe signal int.RAS is set to the inactive state ("L" level). By delaying the internal row address strobe signal int.RAS to the time point t6, the signal RXT attains to the "L" level at time t6.
In response, the level of word line WL0 falls, and the data which has been on the bit line BL is again stored in the memory cell.
By the signals S0N and /S0P obtained by delaying the signal RXT to time point t7, transistors QN and QP of sense amplifier 900 are turned off. Thereafter, precharge circuit 930 is rendered conductive, and bit line BL is again precharged to Vdd/2.
In this manner, the series of operations of activating and inactivating banks are performed by successively delaying internally generated signals, in accordance with externally input commands.
FIG. 19 is a schematic block diagram showing configuration of a control signal generating circuit controlling the conventional bank operation.
When there are banks 0 to N in the SDRAM, control circuits 950 to 970 are provided corresponding to the banks 0 to N, respectively.
Here, control signal generating circuit 950 corresponding to bank0, for example, includes: a delay circuit 952 receiving an internal row address strobe signal int.RAS0 corresponding to bank0, delaying the signal for a period corresponding to t1 to t2 or the period from t5 to t6 in FIG. 18 to output a signal RXT0; a delay circuit 954 receiving the signal RXT0, delaying the signal for a period from t2 to t3 or from t6 to t7 to output a sense amplifier activating signal S0N0; a delay circuit 956 receiving an output from delay circuit 954, delaying the output for a period from t3 to t4 and outputting the delayed signal; and an NAND circuit 958 receiving the signal S0N0 and the output from delay circuit 956 to provide sense amplifier activating signal /S0P0.
Control signal generating circuits 960 to 970 provided corresponding to other banks 1 to N basically have the same configuration as control signal generating circuit 950.
The conventional control signal generating circuit for the SDRAM has the above described configuration, in which a relatively large amount of delay is required of each delay circuit.
When word line WL0 rises, for example, in addition to the capacitances of a large number of memory cells connected to word line WL0, there is extremely high capacitance.cndot.resistance values because of long interconnections in the memory cell array. Therefore, an extremely high time constant is necessary for driving the word line WL0. Accordingly, it takes considerably long time for the word line WL0 to attain the potential level of the corresponding common word line RX0.
Therefore, from the rise of the signal RXT at time t2 until the potential level of word WL0 attains to the potential level of the common word line RXT and the data stored in the memory cell appears as sufficient difference in potential levels on bit line BL, the start of operation of the sense amplifier must be delayed.
Actually, in order to ensure operation margin, it is necessary to defer start of operation of the sense amplifier until time t3.
Similarly, when the word line WL0 falls, from the time t6 when the signal RXT attains to the "L" level, until the potential level of word line WL0 attains to the ground potential (0V) and data re-holding operation to the memory cell is completed, termination of operation of the sense amplifier must be delayed. Actually, in order to ensure operation margin, it is necessary to defer termination of the operation of the sense amplifier until time t7.
From the reasons described above, a delay circuit having relatively large amount of delay is necessary for generating signals for controlling activation and inactivation of the banks. This means that a large area is necessary as an area for forming the delay circuit. Especially in a plural bank configuration such as provided in the SDRAM, a delay circuit is necessary for each bank, which leads to increased chip area.